1. Field of the Invention
The present invention relates to a semiconductor device having a configuration in which a logic circuit and an analog circuit that use outputs from the same internal power supply circuit as power voltage supply sources are provided, and a resting current in the logic circuit can be inspected, and a method for inspecting the semiconductor device.
2. Description of Related Art
Some conventional semiconductor devices including an analog circuit and a digital circuit have a configuration in which an internal power output pad, an analog portion power pad, and a logic portion power pad are provided, and during the assembly of a package, wires are stretched from the three pads to one terminal (leads in the package connected to a pin). The inspection of a resting current in the semiconductor device (inspection for whether or not a resting current is within the standards) is conducted by measuring a consumption current of the logic circuit that has a consumption current smaller than that of the analog circuit in a wafer state (pellet state) before the assembly of the package (before the connection of the wires). With this method, a defective product can be removed at a high probability with a narrow tolerance.
The internal power output pad, an analog portion power pad, and a logic portion power pad can be led out individually as three terminals to be connected outside of the semiconductor device so that the consumption current of the logic circuit can be inspected even after the assembly of the package. However, in this configuration, a one-terminal configuration is divided into a plurality of terminals, which may degrade an electrostatic discharge (ESD) tolerance.
Furthermore, the circuits connected to the three terminals are designed so as to have the same potential. However, due to the disconnection of the external connection, or the noise and the shift of an application timing in an inspection process in which a condition is set for each terminal, a voltage is generated among the three terminals and may break the semiconductor device. Therefore, it is necessary to provide three pads: the internal power output pad, the analog portion power pad, and the logic portion power pad, and form a one-terminal configuration by stretching wires from the three pads to one terminal during assembly of a package.
A method for inspecting a semiconductor integrated circuit as described above (for example, see JP 6(1994)-85030 A) will be described with reference to FIG. 6. FIG. 6 is a plan view showing a configuration of a conventional semiconductor device 220. A semiconductor chip 200a includes an internal power supply circuit 202, an analog circuit 203, and a logic circuit 204. An external power input pad 205 and an internal power output pad 206 are connected to the internal power supply circuit 202. An analog portion power pad 207 is connected to the analog circuit 203, and a logic portion power pad 208 is connected to the logic circuit 204. A lead frame 201 has an external power terminal 209 and an internal power terminal 210.
The external power terminal 209 and the external power input pad 205 are connected through a wire, whereby a voltage is supplied to the internal power supply circuit 202. The internal power supply circuit 202 converts the supplied voltage into a predetermined voltage. The internal power output pad 206 is connected to the internal power terminal 210 through a wire, whereby the voltage converted in the internal power supply circuit 202 is supplied to the internal power terminal 210. The internal power terminal 210 is connected to the logic portion power pad 208 and the analog portion power pad 207 through wires, whereby the voltage converted in the internal power supply circuit 202 is supplied to the logic circuit 204 and the analog circuit 203.
In the semiconductor device 220 as described above, a consumption current flowing to the logic portion power pad 208 is measured before the assembly of a package (before the wire-bonding between the terminal and the pads), whereby the inspection of a resting current in the logic circuit 203 with a narrow standard width can be conducted without being influenced by the analog circuit 203.
According to another method for inspecting a resting current in a semiconductor device, the operations of all the circuits other than the logic circuit 204 are stopped (brought into a state in which no consumption current flows), and conditions are set (voltages are applied) from the outside, using a plurality of signal lines (not shown) simultaneously controlling the logic circuit 204 from the analog circuit 203. By inspecting a resting current as described above, the inspection of only the logic circuit 204 can be conducted without being influenced by the analog circuit 203.
Furthermore, FIG. 7 is a block diagram showing a semiconductor chip 200b before being wire-bonded to a lead frame (not shown) in a semiconductor device with a configuration different from that in FIG. 6. The semiconductor chip 200b has a configuration in which the logic portion power pad 208, the analog portion power pad 207, and the internal power output pad 206 of the semiconductor chip 200a shown in FIG. 6 are connected respectively through wires. The inspection of a wafer (pellet) before the semiconductor chip 200b is wire-bonded to the lead frame of the logic circuit 204 is conducted by newly providing a terminal in the logic circuit 204 or providing a test pad (contact portion provided on the semiconductor chip for applying a voltage from the outside during the inspection of a wafer), applying a voltage, and measuring a consumption current.
However, according to the conventional inspection method shown in FIG. 6, in the package assembly (finished product) after wire-bonding, the internal power output pad 206, the analog portion power pad 207, and the logic portion power pad 208 are wire-bonded to the internal power terminal 210, so that it is difficult to measure a resting current only in the logic circuit 204.
Therefore, even if the inspection on a wafer (pellet) is conducted, a defective product cannot be detected when the defective product occurs in various processes leading to the subsequent package assembly (finished product), for example, due to an assembly stress, damage during an inspection process, damage caused by ESD, and the like.
Furthermore, according to another conventional inspection method as described above, it is necessary to stop the operations of all the circuits other than the logic circuit 204, and the number of terminals and terminal peripheral circuits for setting conditions through signal lines increases, raising the cost. Furthermore, it is difficult in terms of a circuit configuration to bring all the circuits other than the logic circuit 204 into a state in which no consumption current flows, and in the analog circuit 203 whose operation is stopped, other than the logic circuit 204, a leakage current flows to make it difficult to measure a resting current in the logic circuit 204 with good precision.
Furthermore, the inspection of the semiconductor device 200b shown in FIG. 7 has high cost since pads or terminals are provided newly, which makes it difficult to enhance inspection precision.